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Silicon proof of intelligent analog IP design flow for flexible automotive components

 
: Reich, Torsten

Nebel, Wolfgang (Chair) ; European Design Automation Association -EDAA-; IEEE Computer Society, Test Technology Technical Council -TTTC-:
Design, Automation and Test in Europe Conference & Exhibition, DATE 2015. Vol.1 : March 9 - 13, 2015, Grenoble, France
Piscataway, NJ: IEEE, 2015
ISBN: 978-3-9815370-4-8
ISBN: 978-1-4799-6404-8
S.403-404
Design, Automation and Test in Europe Conference & Exhibition (DATE) <18, 2015, Grenoble>
Englisch
Konferenzbeitrag
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
intelligent IP; reuse; design flow; post-layout; optimization; yield

Abstract
In this brief paper we present the successful silicon validation of the Intelligent Analog IP (IIP) design flow applied to the design of a SMART sensor IC for automotive requirements. Using a library of reconfigurable and robust analog IP we fast create parameterized cells up to high complexity levels including the corresponding layouts. This allows us (1) to overcome time consuming handcrafted analog re-design cycles, (2) to include the effects of layout parasitics into the optimization loop, and thus (3) to fast achieve different specifications even for multiple technologies. We show that the IIP design flow leads to a strong improvement of design efficiency, silicon performance, and yield.

: http://publica.fraunhofer.de/dokumente/N-335064.html