Abstract
In this work the processing sequence for an integrated interconnection concept for crystalline silicon thin-films (c-Si TF) is introduced. This concept is designed to reduce cost in the production of large-area crystalline silicon thin-film modules. Combining the advantages of classical thin-film and wafer technologies, a soldering-free interconnection of cells in the module is realized. In order to investigate the interconnection concept, a small scale laboratory process was developed and is discussed here. Mini-modules were fabricated using this processing sequence on silicon on insulator (SOI) wafers with epitaxially grown back surface field (BSF) and base layer. Despite a non-optimized metallization sequence an open circuit voltage of over 3V could be achieved for a mini-module consisting of five cells. Mini-modules were also encapsulated without loss in efficiency after encapsulation.