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Vertical interconnections using through encapsulant via (TEV) and through silicon via (TSV) for high-frequency system-in-package integration

: Wojnowski, M.; Pressel, K.; Beer, G.; Heinig, Andy; Dittrich, Michael; Wolf, Jürgen

Postprint urn:nbn:de:0011-n-3263728 (520 KByte PDF)
MD5 Fingerprint: 21bc10cae5407f53d0502f490105fdfe
Erstellt am: 12.2.2015

Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 16th Electronics Packaging Technology Conference, EPTC 2014. Proceedings : 3-5 December 2014, Singapore
Singapore: Research Publishing, 2014
ISBN: 978-1-4799-6994-4
ISBN: 978-1-4799-6995-1
Electronics Packaging Technology Conference (EPTC) <16, 2014, Singapore>
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
Fraunhofer IZM ()

In this paper we investigate two vertical interconnect options for high-frequency system-in-package (SiP) integration: through encapsulant via (TEV) applied to the embedded wafer level ball grid array (eWLB) technology and through silicon via (TSV). We compare both solutions in terms of size and electrical performance. We use analytic expressions and electromagnetic simulations for our analysis and present measurement results of selected structures for verification. The results show that the choice of TEV and TSV depends on application and cost window.