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Development of process and design criteria for stress management in through silicon vias

: Hölck, Ole; Nuss, Max; Grams, Arian; Prewitz, Tobias; John, Peggy; Fiedler, Conny; Böttcher, Matthias; Walter, Hans; Wolf, M. Jürgen; Wittler, Olaf; Lang, Klaus-Dieter


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 64th Electronic Components and Technology Conference, ECTC 2014 : 27-30 May 2014, Orlando, Florida, USA
Piscataway, NJ: IEEE, 2014
ISBN: 978-1-4799-2406-6
ISBN: 978-1-4799-2407-3
ISBN: 978-1-4799-2408-0
ISBN: 978-1-4799-2407-3
Electronic Components and Technology Conference (ECTC) <64, 2014, Orlando/Fla.>
Fraunhofer IZM ()

In this paper we report experimental results of through silicon vias (TSVs) at an early processing step which are used in a context of reliability assessment. Parameter studies and evaluation of stresses using finite element analysis contribute to an optimization of processing parameters. Our results comprise nanoindentations to characterize copper protrusion, elasticity and hardness from the top as well as on cross-sections into the depth of the TSVs, EBSD analysis of cross-sections to characterize grain size and orientation and seed-layer influence. FIB-images were used to identify failure modes and finite element studies show reasonable agreement to detected stresses and reliability hot spots. Detailed Raman maps are presented as an outlook for further investagtion of stress fields at TSV cross sections. Design criteria to improve the production process are discussed based on the obtained results.