Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Multi-scale simulation flow and multi-scale materials characterization for stress management in 3D through-silicon-via integration technologies - effect of stress on 3D IC interconnect reliability

: Sukharev, Valeriy; Zschech, Ehrenfried


Ho, P.S. ; American Institute of Physics -AIP-, New York:
Stress Induced Phenomena and Reliability in 3D Microelectronics : 28–30 May 2012, Kyoto, Japan
New York, N.Y.: AIP Press, 2014 (AIP Conference Proceedings 1601)
ISBN: 978-0-7354-1235-4
International Workshop on Stress-Induced Phenomena in Microelectronics <12, 2012, Kyoto>
Fraunhofer IKTS ()
compact model; FEA; materials characterization; simulation

The paper addresses the growing need in a simulation-based design verification flow capable to analyze any design of 3D IC stacks and to determine across-layers implications in 3D IC reliability caused by through-silicon-via (TSV) and chip-package interaction (CPI) induced mechanical stresses. The limited characterization/measurement capabilities of 3D IC stacks and a strict "good die" requirement make this type of analysis really critical for the achievement of an acceptable level of functional and parametric yield and reliability. The paper focuses on the development of a design-for- manufacturability (DFM) type of methodology for managing mechanical stresses during a sequence of designs of 3D TSV-based dies, stacks and packages. A set of physics-based compact models for a multi-scale simulation, to assess the mechanical stress across the dies stacked and packaged with the 3D TSV technology, is proposed. As an example the effect of CPI/TSV induced stresses on stress migration (SM) and electromigration (EM) in the back-end-of-line (BEoL) and backside-redistribution-layer (BRDL) interconnect lines is considered. A strategy for a simulation feeding data generation and a respective materials characterization approach are proposed, with the goal to generate a database for multi-scale material parameters of wafer-level and package-level structures. A calibration technique based on fitting the simulation results to measured stress components and electrical characteristics of the test-chip devices is discussed.