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Heterogeneous 3D integration for smart systems

 
: Wolf, M. Jürgen; Lang, Klaus-Dieter

VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik -GMM-; VDI/VDE Innovation+Technik, Berlin:
MikroSystemTechnik Kongress 2013. CD-ROM : Von Bauelementen zu Systemen; 14. - 16. Oktober 2013 in Aachen
Berlin: VDE-Verlag, 2013
ISBN: 978-3-8007-3555-6
ISBN: 3-8007-3555-5
S.192-195
MikroSystemTechnik Kongress <2013, Aachen>
Englisch
Konferenzbeitrag
Fraunhofer IZM ()

Abstract
According to the increasing application driven demands on functionality, performance, miniaturization and reliability for microelectronic systems, System in Packages (SiP) using 3D integration are key elements for advanced micro-electronic packaging. Key elements for 3D wafer level SiPs are the formation of Through Silicon Vias (TSVs) and their process integration into active devices as well as silicon interposer as a key enabler for 3D Systems.

: http://publica.fraunhofer.de/dokumente/N-303668.html