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Scaling and optimization of high-density integrated Si-capacitors

: Weinreich, W.; Seidel, K.; Rudolph, M.; Koch, J.; Paul, J.; Riedel, S.; Sundqvist, J.; Steidel, K.; Gutsch, M.; Beyer, V.; Hohle, C.


Institute of Electrical and Electronics Engineers -IEEE-:
International Semiconductor Conference Dresden-Grenoble, ISCDG 2013 : 26-27 September 2013, Dresden
Piscataway, NJ: IEEE, 2013
ISBN: 978-1-4799-1250-6 (Print)
ISBN: 978-1-4799-1251-3
4 S.
International Semiconductor Conference Dresden-Grenoble (ISCDG) <2013, Dresden>
Fraunhofer IPMS ()

This paper focuses on the scaling and optimization of metal-isolator-metal capacitors integrated in 3D Si structures. Scaling to high capacitance density is aimed by the use of high-k dielectrics and a significant area enhancement realized through silicon pattering with increasing aspect ratios. By material and process optimization the capacitors show excellent IV and CV characteristics with high temperature and reliability performance independently of the 3D structure. A fully functional capacitor of 4mm2 consisting of 80 Mil trenches with an overall capacitance of 850nF can be demonstrated.