Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

A highly reliable flip chip solution based on electroplated AuSn bumps in a leadless package

: Theuss, H.; Pressel, K.; Paulus, S.; Kilger, T.; Dangelmaier, J.; Lehner, R.; Eisener, B.; Kiendl, H.; Schischka, J.; Graff, A.; Petzold, M.

ECTC 2005, the 55th Electronic Components and Technology Conference. Proceedings. CD-ROM : Lake Buena Vista, Florida; May 31-June 3
New York, NY: IEEE, 2005
ISBN: 0-7803-8907-7
Electronic Components and Technology Conference (ECTC) <55, 2005, Lake Buena Vista/Fla..>
Fraunhofer IWM ()
Flip Chip in Package-Konzept; HF-fähige Gehäuse für die Mikroelektronik; Zuverlässigkeit bleifreier Lote; Intermetallische Phase

We introduce an innovative flip chip in package concept based on small electroplated AuSn bumps as first level interconnect. Reliability studies prove the compliance of the leadless package concept to high quality standards, which include moisture sensitivity level 1 (MSL1), temperature cycling on board, shock tests as well as autoclave tests. Detailed SEM and TEM investigations demonstrate an excellent quality of the different interfaces. The package concept meets current packaging requirements, such as small form factor, environmental friendliness (green package), RF capability and low cost production. The flip chip in package concept, demonstrated here for small pin counts, has further potential to be extended to a medium pin count range.