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Advanced 3D packaging of chips and materials integrity: Stress-induced effects and mechanical properties of new ultra low-k dielectrics for on-chip interconnect stacks

: Sander, Christoph; Gall, Martin; Yeap, Kong Boon; Zschech, Ehrenfried


Sandera, P.:
Materials structure & micromechanics of fracture VII : Selected, peer reviewed papers from the 7th International Conference "Materials Structure & Micromechanics of Fracture (MSMF-7)", July 01-03, 2013, Brno, Czech Republic
Durnten-Zurich: TTP, 2014 (Key engineering materials 592/593)
ISBN: 978-303-78593-4-6
ISBN: 978-303-82631-5-9
International Conference "Materials Structure & Micromechanics of Fracture" (MSMF) <7, 2013, Brno>
Fraunhofer IKTS ()
3D integration; indentation; CTE; Young's modulus

Managing the emerging internal mechanical stress in chips particularly if they are 3D-tscked is a key task to maintain performance and reliability of microelectronic products. Hence, a strong need of a physics-based simulation methodology/flow emerges. This physics-based simulation, however, requires materials parameters with high accuracy. A full-chip analysis can then be performed, balancing the need for local resolution and computing time. Therefore, effective composite-type materials data for several regions of interest are needed. Advanced techniques to measure FEA-and design-relevant properties such as local and effective Youngs modulus and effective CTE values were developed and described in this paper. These data show a clear orientation dependence, caused by the chip design.