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Automatic footprint compaction and bond wire placement for bare die chips stacks

 
: Dittrich, Michael; Heinig, Andy; Schneider, Peter

Gessner, T.:
Smart Systems Integration 2014 : Wien/Österreich, 26.3.2014 - 27.3.2014; 8th International Conference and Exhibition on Integration Issues of Miniaturized Systems - MEMS, NEMS, ICs and Electronic Components
Aachen: Apprimus-Verlag, 2014
ISBN: 978-3-86359-201-1
8 S.
Smart Systems Integration Conference (SSI) <2014, Vienna>
International Conference & Exhibition on Integration Issues of Miniaturized Systems - MEMS, NEMS, ICs and Electronic Components <8, 2014, Vienna>
Englisch
Konferenzbeitrag
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Abstract
When designing a SiP with multiple stacked chips as bare die, the SiP designer has to design the substrate footprints of his chip stacks on his own. He needs detailed knowledge of the chip stacking and wire bonding processes and the design rules. Furthermore, he needs to prevent multiple time consuming design iterations. The Paper presents an automatic algorithm which creates a drc valid substrate footprint for a given set of bare die chip stacks. Closing this gap with EDA-tools is an important factor to push this technology.

: http://publica.fraunhofer.de/dokumente/N-292691.html