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3D integration of standard integrated circuits

: Puschmann, R.; Böttcher, M.; Bartusseck, I.; Windrich, F.; Fiedler, C.; John, P.; Manier, C.; Zoschke, K.; Grafe, J.; Oppermann, H.; Wolf, M.J.; Lang, K.D.; Ziesmann, M.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE International 3D Systems Integration Conference, 3DIC 2013 : 2-4 October 2013, San Francisco, Calif.
Piscataway, NJ: IEEE, 2013
ISBN: 978-1-4673-6484-3
7 S.
International 3D Systems Integration Conference (3DIC) <2013, San Francisco/Calif.>
Fraunhofer IZM ()

In this paper we present the process and electrical results of a 3D integration using through silicon vias (TSV). A flash memory chip has been directly connected to a processor die. The TSVs have been applied from the wafer front-side into a fully processed advanced CMOS 300 mm wafers using a via last approach. After dry etching the 20 by 107 mu m holes into the substrate an isolation and barrier seed films are deposited and then filled with copper. The electrical connection between the pad level of the processor chips and the interface to the external connections is realized with a two level redistribution wiring. Subsequently the wafer is flipped, temporary bonded to a carrier wafer, thinned and the TSVs are connected from the wafer backside. Finally the flash chips are assembled to the controller die using a die-to-wafer (D2W) technique. Electrical tests have been conducted and a high yield after TSV processing and assembly determined. The isolation properties and electrical resistance was measured. The linear current in stress transistors was used to define a keep out zone.