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Layout dependent synthesis for manufacturing costs optimized 3D integrated systems

: Heinig, Andy

Postprint urn:nbn:de:0011-n-2872205 (6.5 MByte PDF)
MD5 Fingerprint: b4c3d3691ae47c6e697e165b513fec8c
Erstellt am: 9.7.2014

Institute of Electrical and Electronics Engineers -IEEE-:
IEEE International 3D Systems Integration Conference, 3DIC 2013 : 2-4 October 2013, San Francisco, Calif.
Piscataway, NJ: IEEE, 2013
ISBN: 978-1-4673-6484-3
6 S.
International 3D Systems Integration Conference (3DIC) <2013, San Francisco/Calif.>
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

3D integration opens up entirely new perspectives in chip development, such as integration of different technologies in a stack with smaller form factor as with classical board design. It enables also the partitioning of large SOC designs into a stack with two or more dies. If the resulting 3D-System is optimized, its costs can be smaller than the costs for the manufacturing of the corresponding 2D-System. In this paper a new layout dependent synthesis method for manufacturing costs optimized 3D integrated systems is introduced. As its major part a 3D synthesis optimization method algorithm which used layout information from a floorplanner is presented. The flow was tested on a VLIW processor design, which demonstrates a cost reduction by 3D implementation.