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Double patterning: Simulating a variability challenge for advanced transistors

 
: Evanschitzky, Peter; Burenkov, Alex; Lorenz, Jürgen

:

Institute of Electrical and Electronics Engineers -IEEE-; Univ. Glasgow:
18th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2013 : 3rd - 5th September 2013, Glasgow, Scotland
Piscataway, NJ: IEEE, 2013
ISBN: 978-1-4673-5733-3 (Print)
ISBN: 978-1-4673-5736-4
S.105-108
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) <18, 2013, Glasgow>
European Commission EC
FP7-ICT; 318458; SUPERTHEME
Englisch
Konferenzbeitrag
Fraunhofer IISB ()

Abstract
In this paper a comprehensive study of the impact of variations resulting from double patterning lithography on SRAM performance is presented. In double patterning, feature sizes are reduced by splitting one mask level into two. Besides the increase of process complexity and costs a further penalty is the introduction of uncorrelated variations between the two incremental lithography steps employed.

: http://publica.fraunhofer.de/dokumente/N-283307.html