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An FPGA based cut-through switch optimized for one-step PTP and real-time Ethernet

 
: Flatt, Holger; Jasperneite, Jürgen; Schewe, Frank

:

Institute of Electrical and Electronics Engineers -IEEE-; IEEE Instrumentation and Measurement Society:
ISPCS 2013, International IEEE Symposium on Precision Clock Synchronization for Measurement, Control and Communication. Proceedings : 22-27 September 2013, Lemgo, Germany
Piscataway, NJ: IEEE, 2013
ISBN: 978-1-4799-0241-5 (Print)
ISBN: 978-1-4799-0242-2
ISBN: 978-1-4799-0240-8
S.7-12
International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) <2013, Lemgo>
Englisch
Konferenzbeitrag
Fraunhofer IOSB ()

Abstract
This paper presents an FPGA based Ethernet cut-through switch that is optimized for one-step PTP clock synchronization and fast forwarding of real-time Ethernet frames. Whereas a standard switch ASIC provides sophisticated mechanisms for switching of non-real-time frames, an attached FPGA implements cut-through switching of real-time frames and synchronization events. Moreover, time-stamping of synchronization events, one-step bridge delay compensation, peer-delay responses for power profile and a servo clock are implemented in hardware. The results show that even a low-cost Xilinx Spartan 6 FPGA comprising 47,000 Look-up tables can fulfill the requirements for switching 6 Ethernet ports at 100 Mbps. The combination of cut-through forwarding and transparent one-step clock synchronization yields to bridge delays less than 3 microseconds for both real-time Ethernet data and synchronization events. Therefore, the presented switch can be flexibly integrated into time-synchronized real-time networks in order to provide improved switching functions.

: http://publica.fraunhofer.de/dokumente/N-280038.html