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Adaptive Equalizer Training for High-speed Low-power Communication Systems

: Yuan Fang; Ling Chen; Jaiswal, A.; Hofmann, K.; Gregorius, P.


Matos, J.S.; Leporati, F. ; European Organisation for Information Technology and Microelectronics -EUROMICRO-; Institute of Electrical and Electronics Engineers -IEEE-:
16th Euromicro Conference on Digital System Design, DSD 2013 : Santander, Spain, 4 - 6 September 2013
Los Alamitos: IEEE Computer Society, 2013
ISBN: 978-0-7695-5074-9
ISBN: 978-1-4799-2979-5
Euromicro Conference on Digital System Design (DSD) <16, 2013, Santander>
Fraunhofer HHI ()

In high-speed communication systems, adaptive equalizers are widely applied to improve signal integrity in both master chip and slave chip. In this paper, a novel architecture with the equalizers applied only in the master chip is proposed for the low-power design through adaptive equalizer training. The system architecture is verified by implementing the receiver equalizer training at the circuit level and the transmitter equalizer training using different algorithms: 1) direct calculation 2) LMS algorithm 3) pilot signal/peak detection in Matlab/Simulink. Results show that LMS algorithm improves the vertical and horizontal eye opening by more than 30% and 10%, respectively. Furthermore, the proposed architecture can achieve 411mW per channel, which is a two-fold reduction in the power dissipation with respect to the conventional architecture. To adapt the concept, Graphic DDR5 is taken as a study case.