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Adaptive low-power synchronization technique for multiple source-synchronous clocks in high-speed communication systems

: Jaiswal, A.; Yuan Fang; Gregorius, P.; Hofmann, K.


Matos, J.S.; Leporati, F. ; European Organisation for Information Technology and Microelectronics -EUROMICRO-; Institute of Electrical and Electronics Engineers -IEEE-:
16th Euromicro Conference on Digital System Design, DSD 2013 : Santander, Spain, 4 - 6 September 2013
Los Alamitos: IEEE Computer Society, 2013
ISBN: 978-0-7695-5074-9
ISBN: 978-1-4799-2979-5
Euromicro Conference on Digital System Design (DSD) <16, 2013, Santander>
Fraunhofer HHI ()

Advanced high-speed source-synchronous systems such as GDDR5 use multiple source-synchronous clocks to increase memory bandwidth. Therefore, well-defined phase relationships among multiple clocks are required to perform correct read/write operations. A GDDR5 system solves this problem by adaptive clock synchronization training. For such multiple clocks synchronization training at controller side this paper proposes two simplified architectures based on: a) Unit-delay incrementer, b) PI (Phase-Interpolator) based PLL (Phase-Locked Loop). Experiments show that the proposed unit-delay architecture consumes only 0.89 mW power and 100 (mum) 2 area in 65nm which is 16.8 times less power and 35 times less area than other works while power and area consumed in the PI-based PLL architecture depends upon the complexity of the PI itself.