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Memory access analysis and optimization of a parallel H.264/SVC decoder for an embedded multi-core platform

: Brandenburg, J.; Stabernack, B.

Morawiec, A.; Hinderscheit, J.:
Conference on Design and Architectures for Signal and Image Processing, DASIP 2013
ISBN: 979-10-92279-02-3 (online)
ISBN: 979-10-92279-01-6 (print)
Conference on Design & Architectures for Signal & Image Processing (DASIP) <2013, Cagliari>
Fraunhofer HHI ()

HW/SW co-design and optimization requires an in-depth performance and bottleneck analysis of the developed system. Due to the increasing gap between the performance of the processing elements and the memory subsystem also memory access analysis plays an important role in this optimization task. This is especially the case for state of the art media signal processing applications, like video decoders, with their growing demand for high memory bandwidths and low latency data accesses. Optimizing memory partitioning, memory hierarchy, memory characteristics and allocation of data structures formulates a multidimensional HW/SW co-optimization problem with increasing complexity due to the trend towards embedded multi-core platforms. In order to aid the developer with these optimization tasks, performance and memory access analysis tools are needed. Nowadays there exist many different vendor specific debug and profiling tools for different processor architectures addressing different aspects of the overall co-optimization problem. Moving to heterogeneous platforms makes the combination and integration of the different profiling data a challenging task. Moreover it is important to combine the profiling results with information gathered from dedicated components, like interrupts, signals and/or synchronization events, representing the actual hardware platform. To overcome this issue we propose a flexible tracing and profiling methodology capable to trace all hardware aspects of the modeled simulation platform. Based on this methodology we developed a tool, which gives a comprehensive overview of the software tasks running on the various processing elements of the particular execution platform. Furthermore our tool provides detailed non-intrusive memory access and performance analyses based on SystemC virtual platform simulation models for heterogeneous embedded multi-core platforms. A demonstration of the tools capabilities is given by an exemplary analysis of a Scalable Video Coding (H.264/SVC) decoder application running on a configurable multi-core platform.