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Material limitations due to crucible impurities in multicrystalline silicon for high efficiency solar cells

: Schindler, F.; Michl, B.; Schön, J.; Kwapil, W.; Warta, W.; Schubert, M.C.

Volltext urn:nbn:de:0011-n-2669234 (429 KByte PDF)
MD5 Fingerprint: c8e25a6dd7adc4c4deee3e2099314180
Erstellt am: 30.11.2013

Mine, A. ; European Commission:
28th European Photovoltaic Solar Energy Conference and Exhibition, EU PVSEC 2013. Proceedings. DVD-ROM : 30 September to 04 October 2013, Paris, France
München: WIP-Renewable Energies, 2013
ISBN: 3-936338-33-7
European Photovoltaic Solar Energy Conference and Exhibition (EU PVSEC) <28, 2013, Paris>
Konferenzbeitrag, Elektronische Publikation
Fraunhofer ISE ()
Solarzellen - Entwicklung und Charakterisierung; Silicium-Photovoltaik; Charakterisierung von Prozess- und Silicium-Materialien; Charakterisierung; Qualitätssicherung und Messtechnikentwicklung: Material; Zellen und Module; Impurities; silicon; Defects

For the fabrication of high efficiency silicon solar cells, bulk material with low recombination losses is required. Crystal defects and impurities from feedstock and crucible system harm the electrical material quality of multicrystalline silicon wafers. In this work, spatially resolved efficiency losses in multicrystalline silicon are estimated from injection-dependent bulk lifetime measurements, and the impact of decorated crystal defects, dissolved impurities and impurities diffused into the crystallized silicon by solid-state diffusion is quantified. The high-temperature steps of two solar cell processes, a standard PERC process and a high efficiency approach, are applied to two different p-type multicrystalline silicon materials: One block was crystallized in a G1 sized crucible of industrial material quality and the other in a crucible of very pure electrically fused silica. The high purity wafers allow higher efficiencies than the wafers from the standard crucible after both cell processes and profit from a larger efficiency boost achieved by the high efficiency process. An efficiency gain of 0.5% absolute is estimated to be attainable on wafers including a block edge by using a high purity crucible.