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Characterization and modeling of copper TSVs for silicon interposers

: Malta, D.; Gregory, C.; Lueck, M.; Lannon, J.; Lewis, J.; Temple, D.; DiFonzo, P.; Naumann, F.; Petzold, M.


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 63rd Electronic Components and Technology Conference, ECTC 2013. Proceedings : 28-31 May 2013, Las Vegas, NV, USA
New York, NY: IEEE, 2013
ISBN: 978-1-4799-0233-0 (Print)
ISBN: 978-1-4799-0232-3
Electronic Components and Technology Conference (ECTC) <63, 2013, Las Vegas/Nev.>
Fraunhofer IWM ( IMWS) ()
silicon interposers; 3D-WLP applications; copper TSVs

Silicon interposers enable advanced package architectures through the integration of multiple die and passive components onto a single silicon substrate, while offering high interconnect density and low thermal expansion mismatch. This paper will describe the processing and characterization of copper-filled through silicon vias (TSVs) for Si interposers and related three-dimensional wafer-level packaging (3D-WLP) applications. To evaluate potential reliability concerns, the thermomechanical behavior of Cu-filled TSVs was characterized experimentally over a range of TSV dimensions and also modeled using finite element analysis. The paper will include discussion of the correlation between the experimental observations and modeling data obtained for the TSV structures. Demonstrations of functional Si interposer substrates are also reported, based on three different design variations of TSV diameter and substrate thickness, respectively: 25 × 100m, 50 × 200m, and 80 × 300m. Finally, alternative TSV structures, based on Cu-lined vias with polymer filled cores, are demonstrated as a possible approach to reducing the thermomechanical concerns for Cu-filled TSVs in Si interposer or 3D-WLP substrates.