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Bump on flexible lead for wafer level packaging

: Eidner, I.; Buschick, K.; Dietrich, L.; Pan, K.L.; Minkus, M.; Wolf, M.J.; Ehrmann, O.; Reichl, H.

International Microelectronics and Packaging Society -IMAPS-:
41st International Symposium on Microelectronics 2008 : November 2-6, 2008, Rhode Island Convention Center, Providence, Rhode Island, USA
Reston, Va.: IMAPS, 2008
ISBN: 0-930815-86-6
International Symposium on Microelectronics <41, 2008, Providence/RI>
Fraunhofer IZM ()

A chip-to-substrate interconnect technology is introduced which uses flexible structures to accommodate the CTE mismatch between the chip and PCB substrate and consequently should be reliable without underfill. Increased flexibility, i e. purely elastic response, of the bumps can lead to an increase in the reliability of large Flip Chips. To achieve a high flexibility, the lead-free bump is located on a flexible lead. The flexible lead consists of a copper line embedded in a polymer-bridge which is located over an air gap. For a small bump height, which is necessary to achieve a small package height, the stress due to CTE mismatch is then accommodated within the flexible lead. FEM simulations were performed and prototype chips have been designed and fabricated using wafer level packaging processing methods, such as photolithography, electroplating and wet-etching. The process flow and assembly of the flexible interconnects without underfill are presented and discussed.