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Prospects and yield of electrochemical wafer plating for bumping and signal routing

: Dietrich, L.; Töpper, M.; Fritzsch, Th.; Ehrmann, O.; Reichl, H.

International Microelectronics and Packaging Society -IMAPS-:
EMPC 2007, the 16th European Microelectronics and Packaging Conference & Exhibition. Proceedings. Pt. 2 : June 17 - 20, 2007, Oulu, Finland
Oulu, 2007
ISBN: 978-952-997511-2
European Microelectronics and Packaging Conference and Exhibition (EMPC) <16, 2007, Oulu>
Fraunhofer IZM ()

A micro-electroplating method to fabricate smallest interconnection bumps and highly dense routing layers on semiconductor wafers is being presented and discussed. The single process steps of this wafer-level packaging (WLP) are similar to the machining widely used in front-end technology at the wafer fabs, mainly differing in the structure sizes and layer thicknesses. The process steps as sputtering, lithographical printing, electrochemical metal deposition (ECD), and selective etching are highlighted in detail. Two kinds of a plating base are used for various electrodeposits. They also act as an under-bump metallization (UBM). A sputtered Ti:W(N)/Au seed layer is used for the electroplating of Au and Au/Sn, and a Ti:W/Cu metallization is sputtered for the Cu and Ni/Au deposition as well as for the solder (SnPb37, SnPb5, SnAg3.5, SnCu0.7). Either spin-coating or spraycoating technique is used to deposit the liquid photoresist onto planar or else topography wafers. By a pplying highly viscous and UV sensitive resist systems, layer thicknesses from 5 m up to 120 m with excellent thickness homogeneity and a precise pattern resolution for all standard wafer sizes can be achieved. The commercially available electrolytes have been modified and specially adapted to the micro-electroplatingrequirements. Adequate wet etching solutions had to be specially formulated to minimize the affect and the undercut of the electroplated microstructures.