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Lamination process studies for realisation of chip embedding technologies-current applications and technical challenges

: Manessis, D.; Ostmann, A.; Yen, S.-F.; Aschenbrenner, R.; Reichl, H.

International Microelectronics and Packaging Society -IMAPS-:
EMPC 2007, the 16th European Microelectronics and Packaging Conference & Exhibition. Proceedings. Pt. 1 : June 17 - 20, 2007, Oulu, Finland
Oulu, 2007
ISBN: 978-952-997511-2
European Microelectronics and Packaging Conference and Exhibition (EMPC) <16, 2007, Oulu>
Fraunhofer IZM ()

This paper focuses on the lamination technology employed for the development of a production-capable technology for embedding active chips into printed circuit boards (PCBs). The work is jointly performed by a consortium of partners from industry and research within the frame of the European research project "HIDING DIES". In specific, Resin-Coated-Copper (RCC) films can be laminated on assembled chips and components providing the polymer dielectric matrix for further 3D-SiP package processing. Lamination of RCC films can superbly replace the spin-coating processes. Filled and no-filled epoxy RCC's have been successfully used to laminate very thin (50m) as well as relatively thick chips up to 200m. Pressures from 5 up to 20 bars and heating rates of 3°C/min and 8 °C/min have been used to study the integrity of the resultant interfaces. Lamination at the highest heating rate and pressures of 5 and 10 bar yields interfaces with many voids and a thick epoxy thickness above chip compared to other lamination conditions. Based on shear test results with a shear speed of 100m/sec and shear height of 40m, the low pressures of 5 bar and 10 bar and the highest heating rate result in lower shear strength values than the slowest heating rate of 3 °C/min. Lamination at a pressure of 20 bar yields embedded structures with the highest strength regardless the lamination heating rate chosen. Lamination of a combination of 2-prepreg layers and RCCs with 25m epoxy thickness can achieve embedding of chips with even 200m thickness. Reliability testing of the laminated embedded chips has shown very promising results. Lamination related issues are discussed and lamination process tips are provided for successful chip embedding and further 3D package processing.