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High temperature analog circuit design in PD-SOI CMOS technology using reverse body biasing

: Schmidt, Alexander; Kappert, Holger; Kokozinski, Rainer


Institute of Electrical and Electronics Engineers -IEEE-:
ESSCIRC 2013, 39th European Solid‐State Circuits Conference. Proceedings : Bucharest, Romania; JW Marriott Bucharest Grand Hotel; 16 - 20 September 2013
Piscataway, NJ: IEEE, 2013
ISBN: 978-1-4799-0643-7 (online)
ISBN: 978-1-4799-0644-4
ISBN: 1-4799-0643-3 (online)
European Solid-State Circuits Conference (ESSCIRC) <39, 2013, Bucharest>
Fraunhofer IMS ()
high temperature; PD-SOI; RBB; reverse body biasing; leakage current; gm/id

The analog performance, e.g. intrinsic gain and bandwidth, of SOI (Silicon-on-Insulator) MOSFETs is strongly affected by increasing operating temperature. Increased leakage currents and decreased device performance significantly reduce the high temperature capability of analog circuits at high temperatures. In this paper, we demonstrate that the reverse body biasing (RBB) approach improves the transistor's analog performance up to 400°C. With RBB, operation in the lower moderate inversion region of the SOI transistor is feasible at increased temperatures. The method also allows beneficial FD (fully depleted) device characteristics in a 1.0 µm PD (partially depleted) SOI CMOS process. NHGATE and PHGATE devices with an H-shaped gate have been investigated. Results report an improvement of the gm/Id factor and the intrinsic gain Ai in the moderate inversion region by applying RBB. In addition, essential analog building blocks, e.g. current mirrors, an analog switch and a two-stage operational amplifier have been investigated. It is shown that the high temperature operation of these circuits is significantly enhanced when RBB is applied.