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From wafer level to panel level mold embedding

: Braun, Tanja; Becker, K.-F.; Voges, S.; Thomas, T.; Kahle, R.; Bauer, J.; Aschenbrenner, R.; Lang, K.-D.


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 63rd Electronic Components and Technology Conference, ECTC 2013. Proceedings : 28-31 May 2013, Las Vegas, NV, USA
New York, NY: IEEE, 2013
ISBN: 978-1-4799-0233-0 (Print)
ISBN: 978-1-4799-0232-3
Electronic Components and Technology Conference (ECTC) <63, 2013, Las Vegas/Nev.>
Fraunhofer IZM ()

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-inPolymer) are two major packaging trends in this area. Mold embedding is currently done on wafer level, typically with diameters of 8" to 12", for future process optimization, PCB technologies offer the potential of real large areas up to 610 × 457 mm2. For mold embedding as e.g. for fan-out wafer level packaging compression molding equipment is used in combination with liquid, granular or sheet epoxy molding compounds, with the boundary condition, that mold processes do need a product specific tool (with defined diameter & thickness). Within this paper the potential of tool-less lamination processes, a standard in PCB manufacturing, is evaluated. Lamination is done in panel format using well-known molding compounds from wafer level compression molding. To evaluate the potential of today's encapsulants for large area embedding processes, different liquid, granular and sheet molding compounds have been intensively evaluated on their processability, on process & material induced die shift and on resulting warpage - all on panel level. Acting as an interconnection layer, PCB based redistribution technologies using lamination of resin coated copper (RCC) films are used. Within the paper, different RCC materials are introduced and discussed concerning their reliability potential based on the available layer thicknesses and thermo-mechanical material properties. The feasibility of the proposed technologies is demonstrated using a two chip package. Dies are embedded in panel size by lamination technologies. Subsequently the wiring is done by lamination of an RCC film over the embedded cmponents and on the panel backside for double sided redistribution. In a process flow also similar to conventional PCB manufacturing µvias to the die pads and through mold vias are drilled using a UV laser and are metalized by Cu-electroplating in one step. This way dies are connected to the front copper layer as well as front to backside of the panel. Conductor lines and pads are formed by Cu etching. Finally, a solder mask and a solderable surface finish are applied. If solder depots are necessary, e.g. for BGA packages, those can be applied by solder balling equipment - either by printing or by preform attach. In summary this paper describes the potential to move from wafer level to panel level mold embedding technology in combination with PCB based redistribution processes. The technology described offers a cost effective packaging solution for e.g. single chip packages as well as for future sensor/ASIC systems or processor/memory stacks in volume production.