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Intrinsic MOSFET leakage of high-k peripheral DRAM devices: Measurement and simulation

: Roll, G.; Jakschik, S.; Goldbach, M.; Wachowiak, A.; Mikolajick, T.; Frey, L.


Institute of Electrical and Electronics Engineers -IEEE-:
International Symposium on VLSI Technology, System, and Application, VLSI-TSA 2012. Technical Program. Proceedings : Hsinchu, Taiwan, 23 - 25 April 2012
Piscataway: IEEE, 2012
ISBN: 978-1-4577-2084-0 (electronic)
ISBN: 978-1-4577-2083-3
International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) <2012, Hsinchu>
Fraunhofer IISB ()

The gate leakage (I Gate, table 1) is reduced compared to the conventional 65nm process with SiON dielectric (Fig. 2). The leakage current due to direct tunneling is simulated using the CET as fitting parameter. High-k PFETs with an oxide extension spacer show a decrease in leakage density with reducing channel length, due to an average CET increase of 1Å (Fig. 3). Most likely unintended oxidation of the interlayer at the gate edge by oxygen supply through the spacer causes the CET increase (Fig. 1). The phenomenon is avoided using a nitride extension spacer. But nitride spacers at the inner gate edge are known to lead to increased gate induced drain leakage (GIDL) [8]. A dual oxide nitride extension spacer is sufficient to prevent unintended gate edge oxidation (Fig. 3).