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Copper filling of TSVs for interposer applications

: Jurgensen, N.; Huynh, Q.H.; Engelmann, G.; Ngo, H.-D.; Ehrmann, O.; Lang, K.-D.; Uhlig, A.; Dretschkow, T.; Rohde, D.; Worm, O.; Jager, C.


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 14th Electronics Packaging Technology Conference, EPTC 2012. Proceedings : 5 - 7 December 2012, Resort World Sentosa, Singapore
New York, NY: IEEE, 2012
ISBN: 978-1-4673-4553-8 (Print)
ISBN: 978-1-4673-4551-4 (Online)
Electronics Packaging Technology Conference (EPTC) <14, 2012, Singapore>
Fraunhofer IZM ()

For the electrochemical filling of through silicon vias (TSVs) the geometry of these vias as well as their quantity on the wafer have a severe influence on the electrochemical process parameters, in particular on the current process time profile. So the electrochemical deposition (ECD) current was investigated in dependence of the filling progress, the height-to-depth aspect ratio, and the quantity of high aspect ratio vias on the wafer. The same applies to the number of plating steps at constant current, their length, and the total process time. Valuable insights for the design of via filing recipes could be deduce thereof.