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Buffer schemes for runtime reconfiguration of function variants in communication systems

: Eilers, D.; Steckenbiller, H.; Herkersdorf, A.

Preprint urn:nbn:de:0011-n-243133 (90 KByte PDF)
MD5 Fingerprint: 8371aa86420bee3eaca7abcb12be77bb
Erstellt am: 06.10.2004

Arnold, J. ; IEEE Computer Society, Technical Committee on Computer Architecture:
12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004. Proceedings : 20 - 23 April 2004, Napa Valley, California
Los Alamitos, Calif.: IEEE Computer Society, 2004
ISBN: 0-7695-2230-0
Symposium on Field-Programmable Custom Computing Machines (FCCM) <12, 2004, Napa/Calif.>
Konferenzbeitrag, Elektronische Publikation
Fraunhofer ESK ()
FPGA; dynamic reconfiguration; runtime reconfiguration; function variant; buffer scheme; adaptive signal processing; quality of service; adaptive communication system

This contribution is an extension of our work, which introduced distributed buffer schemes for runtime reconfiguration in adaptive processing architectures, e.g., for streaming media applications. We propose a reconfiguration control protocol and depict results for a reference system implementation. With dynamic reconfiguration, area-cost of field-programmable logic (FPL) can be reduced by reuse, and potential for adaptive signal processing techniques can be enabled. The challenge with runtime reconfiguration is the reconfiguration latency. Given the limitation regarding reconfiguration latency with traditional approaches, we proposed distributed buffer schemes. The simulation results show that our approach enables potential for runtime reconfiguration for adaptive signal processing under real-time constraints. The proposed control protocol enables regular structures for modular based dynamic reconfiguration handling. Finally, we present implementation details and results of an architectural system implementation.