Fraunhofer-Gesellschaft

Publica

Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Design of a 12-bit cyclic RSD ADC sensor interface IC using the intelligent analog IP library

 
: Reich, Torsten

:
Volltext urn:nbn:de:0011-n-2416922 (1.8 MByte PDF)
MD5 Fingerprint: 4f63c488ea69fe423dda55ca33c12dd8
Erstellt am: 23.5.2013


Schneider, Peter (Hrsg.); Klotz, Thomas (Hrsg.) ; Fraunhofer-Institut für Integrierte Schaltungen -IIS-, Institutsteil Entwurfsautomatisierung -EAS-, Dresden:
Dresdner Arbeitstagung Schaltungs- und Systementwurf, DASS 2013. Tagungsband. CD-ROM : 25. - 26. April 2013, Dresden
Stuttgart: Fraunhofer Verlag, 2013
ISBN: 978-3-8396-0545-5
ISBN: 3-8396-0545-8
S.30-35
Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS) <2013, Dresden>
Englisch
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Abstract
Within this paper we present an Intelligent Analog IP design flow and its successful application on an industrial-level mixed-signal ASIC design. This novel design flow is based on a library of flexible (configurable), robust (design for reliability awareness) and technology-independent Analog IPs, available from primitive device level up to complex circuit blocks. Its application leads to a significant increase in efficiency of the overall design process due to reduced design and layout cost, speed-up or even avoidance of redesign cycles and very fast technology porting. For the design of a multi-physical SMART sensor interface with a low-power 12-bit RSD ADC we already saved 43 % of layout time using the Intelligent Analog IP design flow. In addition, system-level and schematic design as well as post-layout verification was more efficient compared to conventional design flows.

: http://publica.fraunhofer.de/dokumente/N-241692.html