Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Design of a 12-bit cyclic RSD ADC sensor interface IC using the intelligent analog IP library

: Reich, Torsten

Preprint urn:nbn:de:0011-n-2384852 (3.1 MByte PDF)
MD5 Fingerprint: b7fa063bf1ebee7bfb42ed237d72239e
Erstellt am: 6.8.2014

Henkel, F. ; VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik -GMM-; Informationstechnische Gesellschaft -ITG-:
ANALOG 2013. Entwicklung von Analogschaltungen mit CAE-Methoden. CD-ROM : Vorträge der 13. ITG/GMM-Fachtagung vom 4. bis 6. März 2013 in Aachen
Berlin: VDE-Verlag, 2013 (ITG-Fachbericht 239)
ISBN: 978-3-8007-3467-2
6 S.
Fachtagung Entwicklung von Analogschaltungen mit CAE-Methoden (ANALOG) <13, 2013, Aachen>
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Within this paper we present an Intelligent Analog IP design flow and its successful application on an industrial-level mixed-signal ASIC design. This novel design flow is based on a library of flexible (configurable), robust (Design for reliability awareness) and technology-independent Analog IPs, available from primitive device level up to complex circuit blocks. Its application leads to a significant increase in efficiency of the overall design process due to reduced design and layout cost, speed-up or even avoidance of redesign cycles and very fast technology porting. For the design of a multi-physical SMART sensor interface with a low-power 12-bit RSD ADC we already saved 43 % of layout time using the Intelligent Analog IP design flow. In addition, system-level and schematic design as well as post-layout verification was more efficient compared to conventional design flows.