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PD-SOI MOSFET performance optimization for high temperatures up to 400°C using reverse body biasing

: Schmidt, Alexander

Henkel, F. ; VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik -GMM-; Informationstechnische Gesellschaft -ITG-:
ANALOG 2013. Entwicklung von Analogschaltungen mit CAE-Methoden. CD-ROM : Vorträge der 13. ITG/GMM-Fachtagung vom 4. bis 6. März 2013 in Aachen
Berlin: VDE-Verlag, 2013 (ITG-Fachbericht 239)
ISBN: 978-3-8007-3467-2
5 Bl.
Fachtagung Entwicklung von Analogschaltungen mit CAE-Methoden (ANALOG) <13, 2013, Aachen>
Fraunhofer IMS ()
high temperature; SOI; leakage current; gm/id

SOI (Silicon-on-Insulator) MOSFET device performance, i.e. intrinsic gain and bandwidth, in a wide temperature range up to 400°C has so far been strongly affected by device leakage currents. Also the moderate inversion region as a desired point of operation has been unusable as leakage currents dominate drain currents at high temperatures. In this paper we present a reverse body-biasing (RBB) approach to reduce leakage currents and simultaneously improve the transistor's performance up to 400°C. Thereby operation in the lower moderate inversion region of the SOI transistor device is feasible. The method presented here allows beneficial FD (fully depleted) device characteristics in a 1.0 µm PD (partially depleted) SOI CMOS process. Split-Source NSOI and NHGATE devices with an H-shaped gate have been investigated. Results report a leakage current reduction of 97% and a 670% improvement of the gm/Id factor in the moderate inversion region the NHGATE device by applying the presented technique.