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Analysis of risks and related damages due to the implementation of virtual metrology algorithms into semiconductor fabrication lines

Presentation held at APC Conference XXIV 2012, 10.09.2012 to 12.09.2012, Michigan
: Koitzsch, Matthias

Volltext urn:nbn:de:0011-n-2281085 (656 KByte PDF)
MD5 Fingerprint: bd49105b3b7e863d75c6c20679ea2774
Erstellt am: 22.2.2013

2012, 2 S.
Advanced Process Control Conference (APC) <24, 2012, Ann Arbor/Mich.>
Vortrag, Elektronische Publikation
Fraunhofer IISB ()
investment assessment; virtual metrology; risk; financial damages

Increasing wafer diameter and decreasing feature sizes demand for reliable and fast process control on wafer level and even within wafer control loops. Virtual Metrology (VM) appears to be the only way to reach the required level of control. VM enables the prediction of physical and electrical device parameters on the wafers from information collected in real time from manufacturing tools. Implementing VM algorithms into existing fab structures will permit to virtually measure all processed wafers, thus improving device quality and yield. A model has been developed to calculate the economic benefits due to the implementation of VM. This model has been extended to consider also potential damages in case the VM algorithms fail. This paper presents the evaluation of potential risks due to the implementation of VM algorithms into existing fabrication lines, providing a valuable and important extension of existing investment assessment.