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Current challenges in interposer and 3D-design

Presentation held at 4th Design for 3D Silicon Integration Workshop 2012, Lausanne, Switzerland
: Wilde, Andreas

Präsentation urn:nbn:de:0011-n-2214271 (3.4 MByte PDF)
MD5 Fingerprint: 4009c73e8c0e516d67cd570280be43ce
Erstellt am: 7.12.2012

2012, 28 Seiten
Design for 3D Silicon Integration Workshop <4, 2012, Lausanne>
Vortrag, Elektronische Publikation
Fraunhofer IIS ()

While 3D integration technologies become more and more mature on the design side several issues still remain. This talk addresses the routing problem for interposers in conjunction with warping and cost. An interposer design according to the new JEDEC 229 wide I/O standard is presented. Furthermore the floorplanning tool for 3D-ICs developed at Fraunhofer IIS/EAS is presented and the work flow is discussed.