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2012
Presentation
Titel
Current challenges in interposer and 3D-design
Titel Supplements
Presentation held at 4th Design for 3D Silicon Integration Workshop 2012, Lausanne, Switzerland
Abstract
While 3D integration technologies become more and more mature on the design side several issues still remain. This talk addresses the routing problem for interposers in conjunction with warping and cost. An interposer design according to the new JEDEC 229 wide I/O standard is presented. Furthermore the floorplanning tool for 3D-ICs developed at Fraunhofer IIS/EAS is presented and the work flow is discussed.