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An FPGA based approach for the enhancement of COTS switch ASICs with real-time Ethernet functions

 
: Flatt, Holger; Schriegel, Sebastian; Jasperneite, Jürgen; Schewe, F.

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University of Science and Technology, Krakow; IEEE Industrial Electronics Society:
17th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2012. Proceedings. Vol.1 : Krakow, Poland, 17 - 21 September 2012
New York, NY: IEEE, 2012
ISBN: 978-1-4673-4735-8 (Print)
ISBN: 978-1-4673-4736-5 (Online)
ISBN: 978-1-4673-4737-2
S.469-472
International Conference on Emerging Technologies and Factory Automation (ETFA) <17, 2012, Kraków>
Englisch
Konferenzbeitrag
Fraunhofer IOSB ()

Abstract
This paper presents an approach for the enhancement of standard switch ASICs with real-time Ethernet functions. Whereas a standard switch ASIC provides sophisticated mechanisms for switching of non real-time frames, an attached FPGA implements cut-through switching of real-time frames. The proposed FPGA architecture supports configuration of port numbers, bandwidth reservation for real-time frames and utilizes flow-control mechanisms of the ASIC in order to keep frame buffer sizes low. Mapping exemplary RTE extensions of PROFINET IRT onto a Xilinx Spartan 6 FPGA demonstrates the capability of providing band-width reservation and cut-throughforwarding of real-time frames. Therefore, the approach benefits from the innovations made by the switch manufacturers, whereas only a small amount of functions has to be mapped onto an FPGA.

: http://publica.fraunhofer.de/dokumente/N-219620.html