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PUF-based secure test wrapper design for cryptographic SoC testing

 
: Das, A.

Preas, K. ; European Design Automation Association -EDAA-; Institute of Electrical and Electronics Engineers -IEEE-:
Design, Automation & Test in Europe Conference & Exhibition, DATE 2012. Vol.1 : Dresden, Germany, 12 - 16 March 2012; proceedings
Piscataway/NJ: IEEE, 2012
ISBN: 978-3-9810801-8-6
ISBN: 978-1-4577-2145-8
S.866-869
Design, Automation and Test in Europe Conference & Exhibition (DATE) <15, 2012, Dresden>
Englisch
Konferenzbeitrag
Fraunhofer SIT ()

Abstract
Globalization of the semiconductor industry increases the vulnerability of integrated circuits. This particularly becomes a major concern for cryptographic IP blocks integrated on a System-on-Chip (SoC). The trustworthiness of these cryptographic blocks can be ensured with a secure test strategy. Presently, the IEEE 1500 Test Wrapper has emerged as the test standard for industrial SoCs. Additionally a secure activation mechanism has been proposed to this standard in order to restrict access to the testing interface to eligible testers by using a cryptographic authentication mechanism. This access mechanism is necessary in order not to provide any side-channels which may leak secret information for attackers. However, this approach requires the authentication mechanism to be implemented in hardware incurring an area overhead, and the authentication secrets to be securely stored in non-volatile memory (NVM), which may be susceptible to side-channel attacks. In this work, we enhance the secure test wrapper allowing testing of multiple IP blocks using a PUF-based authentication mechanism which overcomes the necessity of secure NVM and reduces the implementation overhead.

: http://publica.fraunhofer.de/dokumente/N-206470.html