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Compilation of methodologies to speed up the verification process at system level

 
: Radke, Stephan; Rülke, Steffen; Oliveira, Marcio F.S.; Kuznik, Christoph; Müller, Wolfgang; Ecker, Wolfgang; Esen, Volkan; Hufnagel, Simon; Bannow, Nico; Brazdrum, Helmut; Janssen, Peter; Le, Hoang M.; Große, Daniel; Drechsler, Rolf; Fehlauer, Erhard; Koch, Gernot; Burger, Andreas; Bringmann, Oliver; Rosenstiel, Wolfgang; Haedicke, Finn; Görgen, Ralph; Oetjens, Jan-Hendrik

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Postprint urn:nbn:de:0011-n-2054270 (374 KByte PDF)
MD5 Fingerprint: b4d630d94e568820f1056f3e33904c82
Erstellt am: 22.8.2014


Bundesministerium für Bildung und Forschung -BMBF-; Electronic Design Automation Centrum -edacentrum-, Hannover:
EdaWorkshop 2012. Tagungsband : Hannover, 8. - 9. Mai 2012; Band 1: Tagungsband; Band 2: Vortragsfolien der Projektvorträge
Berlin: VDE-Verlag, 2012
ISBN: 978-3-8007-3428-3
ISBN: 3-8007-3428-1
S.57-62
edaWorkshop <6, 2012, Hannover>
Englisch
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Abstract
This paper describes the ongoing research of significant performance enhancements in the simulation-based verification process at electronic system level. In this challenging field, there is more than one way to improve the verification process. Hence, a compilation is presented which contains seven novel or enhanced approaches respectively.
Each of it addresses another subdomain in the field of simulation-based verification. Every individual approach targets to reduce the process time in that subdomain. Utilizing them united, the approaches afford a significant performance benefit.
Most of this work has been accomplished in the SANITAS project that is partly funded by the German Federal Ministry of Education and Research (BMBE).

: http://publica.fraunhofer.de/dokumente/N-205427.html