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Trench gate integration into planar technology for reduced on-resistance in LDMOS devices

: Erlbacher, T.; Rattmann, G.; Bauer, A.J.; Frey, L.

Institute of Electrical and Electronics Engineers -IEEE-:
22nd International Symposium on Power Semiconductor Devices & IC's, ISPSD 2010 : 6-10 June 2010, Hiroshima, Japan
New York, NY: IEEE, 2010
ISBN: 978-1-4244-7718-0
ISBN: 978-4-88686-069-9
International Symposium on Power Semiconductor Devices and ICs (ISPSD) <22, 2010, Hiroshima>
Fraunhofer IISB ()

In this paper, we report on the reduction of device resistance by up to 49% in junction isolated lateral double diffused metal-oxide-semiconductor (LDMOS) field effect transistors by incorporating trench gates into conventional planar technology. The process and device simulations of this novel device topology are based on different state-of-the-art LDMOS field effect transistor concepts with and without a reduced surface field extension (buried p-well) for high voltage applications used for standard IC and ASIC manufacturing processes in commercially available foundry processes. A limited number of additional process steps are required for manufacturing such a device, and the well implants can remain unchanged. By a straight-forward combination of trench gate with planar gate topology the device resistance can be reduced from 217m down to 110m for an underlying 50V LDMOS device with a 3.3V gate oxide. The robustness of trench gate integration into existing planar gate technology is demonstrated by fully maintaining the specified blocking properties.