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Silicon interposer for heterogeneous integration

: Wolf, M.J.; Zoschke, K.; Wieland, R.; Klein, M.; Lang, K.-D.; Reichl, H.

Surface Mount Technology Association -SMTA-:
Pan Pacific Microelectronics Symposium and Tabletop Exhibition 2010 : Kauai, Hawaii, 26 - 28 January 2010
Red Hook, NY: Curran, 2010
ISBN: 978-1-615-67947-8
Pan Pacific Microelectronics Symposium <2010, Kauai/Hawaii>
Fraunhofer IZM ()

Heterogeneous integration is one of the key topics for future system integration to address today's requirements of smart electronic systems in terms of performance, functionality, miniaturization, low production cost and time to market. The traditional microelectronic packaging will more and more convert into complex system integration. 'More than Moore' will be required due to tighter integration of system level components at the package level. This trend leads to advanced 3D System in Package solutions (SiP). One of the most promising technology approaches is 3D packaging which involves a set of different integration approaches. Silicon interposer with TSV's offers a new possibility to merge advanced devices e.g. high pin count ASICs, memories and MEMS using a silicon interposer with Through Silicon Vias (TSVs). Two applications using a Si Interposer are described in this paper. One of the key advantages of this approach is the integration of passive components (resistors, capacitors, inductors, etc.) close to the active dice which results in minimal parasitic.