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Characterization and failure analysis of TSV interconnects: From non-destructive defect localization to material analysis with nanometer resolution

 
: Krause, M.; Altmann, F.; Schmidt, C.; Petzold, M.; Malta, D.; Temple, D.

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Preprint urn:nbn:de:0011-n-1896528 (5.2 MByte PDF)
MD5 Fingerprint: 769958d04f025402317a05e57293573c
© 2011 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Erstellt am: 16.10.2012


IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 61st Electronic Components and Technology Conference, ECTC 2011 : Lake Buena Vista, Florida, USA, 31 May - 3 June 2011; 2011 proceedings
Piscataway/NJ: IEEE, 2011
ISBN: 978-1-61284-497-8 (Print)
ISBN: 978-1-61284-498-5
ISBN: 978-1-61284-496-1
S.1452-1458
Electronic Components and Technology Conference (ECTC) <61, 2011, Lake Buena Vista/Fla.>
Englisch
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IWM ( IMWS) ()

Abstract
In this paper different methods and novel tools for nondestructive failure localization and high resolution material analysis in 3D integrated devices will be discussed. The employed methodologies combine non-destructive fault localization with efficient and accurate target preparation to gain access for the following microstructure analysis, forming a subsequent failure analysis workflow. The concepts presented here involve the application of improved Lock-In Thermography (LIT) as well as different innovative concepts of high rate Focused Ion Beam (FIB) techniques and high resolution material characterization utilizing Electron Backscatter Diffraction (EBSD) and Transmission Electron Microscopy (TEM) with Nanospot Energy Dispersive X-ray Spectroscopy (EDS). In the first part of the paper the potential and the advantages of each of the techniques will be demonstrated with respect to their application for Through Silicon Via (TSV) technologies by means of different case studies. To illustrate the complete workflow of the approach, a failure analysis of a vertically integrated microsystem using a micro-bump technology is described in the second part.

: http://publica.fraunhofer.de/dokumente/N-189652.html