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Stress analysis during assembly and packaging

: Schreier-Alt, T.; Unterhofer, K.; Ansorge, F.; Lang, K.-D.


IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 61st Electronic Components and Technology Conference, ECTC 2011 : Lake Buena Vista, Florida, USA, 31 May - 3 June 2011; 2011 proceedings
Piscataway/NJ: IEEE, 2011
ISBN: 978-1-61284-497-8 (Print)
ISBN: 978-1-61284-498-5
ISBN: 978-1-61284-496-1
Electronic Components and Technology Conference (ECTC) <61, 2011, Lake Buena Vista/Fla.>
Fraunhofer IZM ()

This paper investigates stress and strain within electronic systems during fabrication and reliability testing. The paper presents results of a new on-chip CMOS stress measurement technology. We investigated stresses during microelectronic packaging and reliability testing. Special focus is on transfer molding, stress during temperature change and during reliability tests. Experimental results are compared with numerical simulations. The stress sensor is based on a CMOS chip, subdivided into 60 measurement cells (300m grid) and needs only four electrical connections. We are able to measure the shear and both main stresses in-plane of the chip surface. The stress value of the measurement cell can be interrogated subsequently within 16 ms time steps. The main potential of this stress measurement chip is to replace selected electronic parts and to investigate all production and lifetime related loads acting on the system. The presented measurement technique enables a more accurate characterization of manufacturing processes and polymers' behavior. Finally the sensor enables the choice of optimized materials minimizing production related stresses and leading to more reliable products.