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3D Sensor application with open through silicon via technology

 
: Kraft, J.; Schrank, F.; Teva, J.; Siegert, J.; Koppitsch, G.; Cassidy, C.; Wachmann, E.; Altmann, F.; Brand, S.; Schmidt, C.; Petzold, M.

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Preprint urn:nbn:de:0011-n-1896356 (1.2 MByte PDF)
MD5 Fingerprint: 705fdeef4a56dbd4cc7fbcd9d33a5ac2
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Erstellt am: 13.10.2012


IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 61st Electronic Components and Technology Conference, ECTC 2011 : Lake Buena Vista, Florida, USA, 31 May - 3 June 2011; 2011 proceedings
Piscataway/NJ: IEEE, 2011
ISBN: 978-1-61284-497-8 (Print)
ISBN: 978-1-61284-498-5
ISBN: 978-1-61284-496-1
S.560-566
Electronic Components and Technology Conference (ECTC) <61, 2011, Lake Buena Vista/Fla.>
Englisch
Konferenzbeitrag, Elektronische Publikation
Fraunhofer IWM ( IMWS) ()

Abstract
Today 3D interconnection approaches are considered to provide one of the most promising enabling technologies for More than Moore solutions. In particular, 3D integration can provide significant progress in semiconductor device development regarding increased system functionality and integration density. In this paper, we describe an innovative concept for sensor integration based on a quality-proven open TSV technology on the basis of a 0.35m CMOS process. An application-optimized sensor-layer is processed on a specific wafer substrate, whereas the CMOS circuits of the system can remain cost-efficiently on an appropriate 0.35m CMOS or HV-CMOS technology. Another advantage of the proposed TSV solution is the geometric aspect. As the CMOS is attached to the sensor backside, almost 100% of the chip area can be used for the sensing functionality. In the presented technological approach, the sensor wafer is finalized with processing a top metal layer and successive bond oxi de layers. The bond oxide layers are planarized by chemo mechanical polishing (CMP). The CMOS wafer is fabricated using a regular 0.35m CMOS technology up to the vias before the last metal layer. A nitride layer is deposited in order to protect the integrated circuits from damages during the back grinding process. Prior to bonding, the CMOS wafer is thinned down to a thickness of 250m and then bonded to the sensor wafer by plasma activated bonding followed by an annealing step to reinforce the bond strength. TSV etching is sequentially performed in three steps: firstly, the oxide of inter-metal dielectrics is opened. Secondly, the bulk silicon of the CMOS wafer is etched using a deep reactive ion etch (DRIE) process selectively stopping on the bond oxide of the sensor wafer. After several cleaning steps the spacer oxide is deposited followed by the spacer and bond oxide etching. For TSV metallisation, Tungsten as deposited in a CVD process is chosen providing uniform conformal coating inside the ope

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