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Aspects of chip/package interaction and 3-D integration assessed by the investigation of crack and damage phenomena in low-k BEoL stacks

: Auersperg, J.; Rzepka, S.; Michel, B.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 14th International Interconnect Technology Conference and Materials for Advanced Metallization, IITC/MAM 2011 : Dresden, Germany, 8 - 12 May 2011
New York, NY: IEEE, 2011
ISBN: 978-1-4577-0503-8
ISBN: 978-1-4577-0501-4
ISBN: 1-4577-0501-X
ISBN: 978-1-4577-0502-1
International Interconnect Technology Conference (IITC) <14, 2011, Dresden>
Materials for Advanced Metallization Conference (MAM) <20, 2011, Dresden>
Fraunhofer ENAS ()

Miniaturization and increasing functional integration push the development of feature sizes of advanced CMOS down to the nanometer range. New low-k and ultra low-k materials in Back-end of line (BEoL) structures cause new challenges for reliability analysis and prediction, in addition. A combined numerical/experimental approach will be explained towards optimizing fracture and fatigue resistance of BEoL-structures by making use of bulk and interface fracture concepts. The risk of near-chip-edge and near-bump cracking in BEoL-structures with lead-free as well as copper-pillar interconnects is analyzed and optimized under chip package interaction (CPI) and FC-reflow-soldering, in particular.