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Electrical property improvements of ultra low-k ILD using a silylation process feasible for process integration

 
: Thomas, O.; Schaller, M.; Gerlich, L.; Fischer, D.; Leppack, S.; Bartsch, C.; Schulz, S.E.

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Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 14th International Interconnect Technology Conference and Materials for Advanced Metallization, IITC/MAM 2011 : Dresden, Germany, 8 - 12 May 2011
New York, NY: IEEE, 2011
ISBN: 978-1-4577-0503-8
ISBN: 978-1-4577-0501-4
ISBN: 1-4577-0501-X
ISBN: 978-1-4577-0502-1
S.22-24
International Interconnect Technology Conference (IITC) <14, 2011, Dresden>
Materials for Advanced Metallization Conference (MAM) <20, 2011, Dresden>
Englisch
Konferenzbeitrag
Fraunhofer CNT ()
Fraunhofer ENAS ()

Abstract
In this paper the effect of a vapor phase based silylation process on patterned test structures using ULK based ILD's was investigated. It was found that the resistance to capacitance (RC) behavior can be improved. This improvement was found to be scalable, meaning with decreasing metal pitch the RC improvement increases. The silylation process provides in addition a decrease of the leakage current and was found to have adequate defectivity. As the process is feasible for production and the improvement of the electrical properties increases with smaller feature size, it can be assumed that extra costs of the restoration process will be paid out for future technology nodes, if ULK as an ILD is used.

: http://publica.fraunhofer.de/dokumente/N-189453.html