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Reliability testing and failure analysis of 3D integrated systems

 
: Klumpp, A.; Ramm, P.; Franz, G.; Rue, C.; Kwakman, L.

:

Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 14th International Interconnect Technology Conference and Materials for Advanced Metallization, IITC/MAM 2011 : Dresden, Germany, 8 - 12 May 2011
New York, NY: IEEE, 2011
ISBN: 978-1-4577-0503-8
ISBN: 978-1-4577-0501-4
ISBN: 1-4577-0501-X
ISBN: 978-1-4577-0502-1
S.220-222
International Interconnect Technology Conference (IITC) <14, 2011, Dresden>
Materials for Advanced Metallization Conference (MAM) <20, 2011, Dresden>
Englisch
Konferenzbeitrag
Fraunhofer EMFT ()

Abstract
3D integration comes with the introduction of many new processes and materials that may affect behavior and reliability of the overall system. For reliability testing of 3D integration technologies a 3-level test chip has been designed that includes Through Silicon Vias (TSV's) and assembly layers and that allows evaluation of yield and electrical parameters under steady state (DC) and RF signal conditions. Additionally, this (stacked) chip delivers reliability values when used within the standardized procedures defined by JDEC. Subsequent Physical Failure Analysis has been performed using a novel plasma-FIB system that allows efficient chip access and first line analysis thanks to its high mill rates and good image resolution. In this paper, the test chip design, reliability testing and physical analysis details will be presented.

: http://publica.fraunhofer.de/dokumente/N-189450.html