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Multi-scale simulation methodology for stress assessment in 3D IC

Effect of die stacking on device performance
: Sukharev, V.; Kteyan, A.; Choy, J.-H.; Hovsepyan, H.; Markosian, A.; Zschech, E.; Huebner, R.


Journal of electronic testing. JETTA 28 (2012), Nr.1, S.63-72
ISSN: 0923-8174
Fraunhofer IZFP, Institutsteil Dresden ( IKTS-MD) ()

Potential challenges with managing mechanical stress distributions and the consequent effects on device performance for advanced 3D integrated circuit (IC) technologies are outlined. A set of physics-based compact models for a multi-scale simulation, to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 3D through-silicon-via (TSV) technology, is proposed. A calibration technique based on fitting to measured stress components and electrical characteristics of the test-chip devices is presented. For model validation, high-resolution strain measurements in Si channels of the test-chip devices are needed. At the nanoscale, the transmission electron microscopy (TEM) is the only technique available for sub-10 nm strain measurements so far.