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A stochastic method for security evaluation of cryptographic FPGA implementations

: Kasper, M.; Schindler, W.; Stöttinger, M.


Bian, J. ; Institute of Electrical and Electronics Engineers -IEEE-, Beijing Section:
International Conference on Field-Programmable Technology, FPT 2010 : Beijing, China, 8 - 10 December 2010
Piscataway/NJ: IEEE, 2010
ISBN: 978-1-4244-8980-0
ISBN: 978-1-4244-8983-1
ISBN: 978-1-4244-8982-4
ISBN: 978-1-4244-8981-7
International Conference on Field-Programmable Technology (FPT) <9, 2010, Beijing>
Fraunhofer SIT ()

We introduce a stochastic method for the security evaluation and dynamic power consumption analysis in the context of side-channel analysis. This method allows to estimate data-dependent power consumption induced by secret parameters, e.g. a cryptographic key, which may be exploited in power attacks. In particular, IP-cores for security applications on FPGAs have to be made secure against these attacks. We show that the same stochastic methods provide FPGA designers constructive feedback on the information leakage of the design. Applied as a constructive tool these stochastic methods allow the designer to quantify the side-channel resistance and weaknesses of the IP-core design, a feature which supports the design of secure and side-channel resistant implementations, especially on FPGAs.