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WLCSP technology direction

: Töpper, M.; Claw, V.; Zoschke, K.; Ehrmann, O.; Reichl, H.

Advancing microelectronics 33 (2006), Nr.1, S.8-12
ISSN: 2222-8748
Fraunhofer IZM ()

As the complexity of devices and systems is rapidly increasing new packaging technologies play a mayor role for the electronic industry as they determine the size, weight, ease of use, durability, reliability, performance and cost of electronic products. As a consequence for miniaturization, area consuming single chip packages are not useful anymore. Therefore Chip Size Packaging (CSP) has been successfully developed since the 1990s. For further cost reduction, the concept of Wafer Level Packaging (WLP) was established. In contrast to pure wafer bumping, it guarantees the SMT assembly process which is not possible for highest pin count microprocessor without additional interposer based packages. Wafer Level Packaging is unique among all different packaging technology as the processes are done on the wafer prior to singulation. Within years, wafer level packaging has been implemented into manufacturing world-wide, mainly based on thin film redistribution. 3-D stacking te chnologies and the integration of passive components based on thin film processes will further push WLP to a higher degree of integration. The industry-wide migration from WLP to System in Packaging (SiP) and Hetero System Integration will benefit from the flip chip and wafer bumping infrastructure which is currently being created at a breathtaking pace because process technology, process equipment and materials, and the general mode of thinking bear many similarities.