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Evaluation of parallel design patterns for message processing systems on embedded multicore systems

Presentation held at SFMA 2011, Salzburg, Austria
: Strebelow, Ronald; Prehofer, Christian

Volltext urn:nbn:de:0011-n-1862579 (969 KByte PDF)
MD5 Fingerprint: b324b69deb676666182821d5a83bfa36
Erstellt am: 8.12.2011

2011, 6 S.
Workshop on Systems for Future Multi-Core Architectures (SFMA) <2011, Salzburg>
Vortrag, Elektronische Publikation
Fraunhofer ESK ()
parallel design patterns; performance evaluation

Software design patterns reect software engineering practices and experience by documenting proven design solutions. Today these patterns cover many areas including concurrent systems as well as systems for message processing. Some examples, like Half-Sync/Half-Async or Proactor patterns, aim for effcient processing of messages in concurrent environments.
While performance evaluations for particular patterns are available in literature there is little work to analyze the multicore performance of these in realistic settings. In this paper we address this problem by evaluating a set of patterns designated for e\'0ecient and concurrent message processing. Through measurement we will show that these patterns have signifcant differences in their performance and that a wrong multi-threading architecture can do more harm than good. Also, we will see that message reception should be distributed over multiple threads.