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Modeling and experimental results of short channel annular MOS transistors

: Lopez, P.; Blanco-Filgueira, B.; Hauer, J.


Institute of Electrical and Electronics Engineers -IEEE-:
ECCTD 2011, 20th European Conference on Circuit Theory and Design : August 29-31, 2011 in Linköping, Sweden
Piscataway/NJ: IEEE, 2011
ISBN: 978-1-4577-0616-5
ISBN: 1-4577-0616-4
ISBN: 1-4577-0617-2
ISBN: 978-1-4577-0617-2
ISBN: 978-1-4577-0618-9
European Conference on Circuit Theory and Design (ECCTD) <20, 2011, Linköping>
Fraunhofer IIS ()

The reduction of the oxide thickness in advanced CMOS processes is one of the many advantages of technology downscaling, as it favors the reduction of the threshold voltage shifts due to radiation-induced gate oxide trapped charge. This inherent radiation hardness of deep submicron processes can be further exploited using gate-enclosed layout transistors with an annular design. In this paper we present a 2-D analytical I-V model for short-channel annular devices based on the solution of the Poisson equation in cylindrical coordinates and a simplified threshold voltage roll-off geometrical model.