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Low-latency histogram equalization for infrared image sequences - a hardware implementation

: Schatz, V.

Preprint urn:nbn:de:0011-n-1745340 (986 KByte PDF)
MD5 Fingerprint: e8d0e775d2915d20112dfb69625b755b
The original publication is available at
Erstellt am: 20.7.2011

Journal of real-time image processing 8 (2013), Nr.2, S.193-206
ISSN: 1861-8200
ISSN: 1861-8219
Zeitschriftenaufsatz, Elektronische Publikation
Fraunhofer IOSB ()
histogram equalization; CLAHE; infrared images; FPGA design; partial dynamic reconfiguration

This work describes a hardware implementation of the contrast-limited adaptive histogram equalization algorithm (CLAHE). The intended application is the processing of image sequences from high-dynamic-range infrared cameras. The variant of histogram equalization implemented is the one most commonly used today. It involves dividing the image into tiles, computing a transformation function on each of them, and interpolating between them. The contrastlimiting is modified to facilitate the hardware implementation, and it is shown that the error introduced by this modification is negligible. The latency of the design is minimized by performing its successive steps simultaneously on the same frame and by exploiting the vertical blank pause between frames. The resource usage of the histogram equalization module and how it depends on its parameters has been determined by synthesis. The design has been synthesized and tested on a Xilinx FPGA. The implementation supports substituting other dynamic range reduction modules for the histogram equalization component by partial dynamic reconfiguration.