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Measurement of thermally induced strains on flip chip and chip scale packages

: Vogel, D.; Kaulfersch, E.; Simon, J.; Kuehnert, R.; Schubert, A.; Michel, B.

Kromann, G.B. ; IEEE Components, Packaging, and Manufacturing Technology Society:
Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2000. Vol.2 : Las Vegas, May 23 - 26, 2000
Piscataway, NJ: IEEE, 2000
ISBN: 0-7803-5912-7
ISBN: 0-7803-5913-5
ISBN: 0-7803-5914-3
Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm) <7, 2000, Las Vegas>
Fraunhofer IZM ()

The authors developed and made use of the microDAC deformation measurement technique to determine strain fields on thermally stressed, cross sectioned FC and CSP specimens. The method allows to resolve strain fields inside tiny structures like e.g. solder interconnects or conductive adhesive layers. It bases on comparison of digitized micrographs obtained from different object load states. Optical, SEM and laser scanning microscopy are applied for image capture. The paper presents results of strain analysis in interconnects of different flip chip configurations and chip scale package types. E.g., global shear of outward bumps is almost completely suppressed in most of flip chip cases by underfilling. Furthermore, bump deformation can be strongly influenced by the local appearance of glass fabrics in organic laminates used as board materials. A main demand to chip scale package reliability is the avoidance of too large thermal solder ball strains, which lead to material fatigue. Different packages with rigid and flex interposers tackle the stress compensation problem in a different way. A first attempt is made to compare some of them basing on experimental strain and warpage measurements.